Business Wire

Imperas Empowers RISC-V Community with riscvOVPsim

Imperas leading commercial simulation technology available for free with RISC-V Open Virtual Platform Simulator (riscvOVPsim™) for RISC-V software development, compliance and DV test developments RISC ...
Semiconductor Engineering

Gem5 Simulation Environment With Customized RISC-V Instructions for LIM Architectures

A new technical paper titled “Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures” was published by researchers at National Tsing-Hua University, Politecnico ...
Business Wire

Cobham Gaisler Successfully Verifies Its First RISC-V Processor, NOEL-V, Using Aldec’s Riviera-PRO for HDL Simulation

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, today announced that Cobham Gaisler has ...
Semiconductor Engineering

Fault Injection Framework Targets RISC-V Security Weak Spots

Researchers from Politecnico di Torino and CEA-List published a technical paper titled “InjectV: Modeling Fault Injection Attacks in RISC-V Simulation Environment.” “Fault Injection Attacks (FIAs) are ...
EDN

Building your own RISC simulator

The process of design, development and testing of a processor takes a long time, during which many models are made to fine-tune its functionality and performance. These models simulate the processor ...
EDN

RISC-V basics: The truth about custom extensions

The era of universal processor architectures is giving way to workload-specific designs optimized for performance, power, and scalability. As data-centric applications in artificial intelligence (AI), ...